Design of Memcapacitive Neuromorphic Circuits for Adaptive Edge AI

RESEARCH OPPORTUNITY

The electronic von Neumann architecture, characterized by the physical separation between memory and computing units, has reached its energy limits, hindering the emergence of an edge AI capable of adapting to its environment. Neuromorphic electronics based on Spiking Neural Networks (SNNs) and the In-Memory Computing (IMC) paradigm stand as the leading solution to overcome this bottleneck. While researchers have so far favored resistive IMC using memristors, this approach faces physical barriers when scaling up: high static currents, Joule heating losses, leakage, and voltage drops (IR drop). The Laboratory of Technologies for Microelectronics (LTM) and the Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) laboratory propose a paradigm shift towards capacitive IMC via voltage summation, enabled by the emergence of ferroelectric capacitive memories (memcapacitors). Operating in the charge domain, these devices eliminate static consumption and open the way to novel bio-plausible learning rules that cannot be achieved with memristors. We are seeking a postdoctoral researcher specialized in neuromorphic circuit design and emerging memories to lead a 24-month project aiming to open a new route towards ultra-low-energy adaptive edge AI.

SCIENTIFIC CHALLENGES

Within a consortium gathering LTM, TIMA and CEA-Leti, you will lead the following tasks:
• Behavioral modeling of ferroelectric memcapacitors by fitting statistical experimental data of Metal-Ferroelectric-Metal capacitors based on Gd:HfO₂ (LTM) and HZO (CEA-Leti). The model written in Verilog-A will account for the capacitive memory window, multi-level programming and device non-idealities.
• Circuit-system co-design for inference by voltage summation in Cadence Virtuoso, using an industrial 130 nm CMOS PDK. You will design complete SNN inference circuits: voltage pulse generators, differential memcapacitive synapses arranged in selector-free crossbars providing signed weights, capacitive IMC based on voltage summation, and current mirrors converting voltages into input currents for the LIF neurons. Simulations will include parasitics and non-idealities through the memcapacitor device models, ensuring realistic performance and energy predictions. You will optimize energy per synaptic operation through transistor sizing and minimization of capacitive loading, with special attention to parasitic coupling when scaling up arrays. In parallel, you will participate in the development in Python of hardware-aware system-level SNN simulations exploiting capacitive synapses.
• Development of novel bio-plausible learning using the system-level simulations, via elaboration of three-factor learning mechanisms natively exploiting memcapacitive physics: pre- and post-synaptic eligibility traces with exponential decay, an asymmetric modulation signal, and the superposition of the three signals to drive capacitive synaptic programming. You will carry out the circuit transcription of this rule up to a 4×4 crossbar demonstration, through an iterative circuit-system co-design loop.

AN EXCEPTIONAL ENVIRONMENT IN EUROPE

The postdoc will take place jointly at LTM and TIMA, in the heart of Europe's largest R&D hub for nanotechnologies.
Technology platforms: At TIMA, you will have direct access to Cadence Virtuoso, an industrial PDK of CMOS 130 nm technology node as well as SPICE-Python co-simulation tools to assess SNN learning and circuit performance. At LTM, you’ll have access to the PTA/CIME Nanotech ecosystem with state-of-the-art electrical characterization tools.
Network and collaborations: You will work with a group of world-class researchers and MSc/PhD students at LTM, TIMA and CEA-Leti with expertise covering device measurements, neuromorphic circuit engineering and SNN learning mechanisms. You will also have the opportunity to develop new projects and mentor research interns.
Dissemination: results will be published in rank-A journals and presented during international conferences.

Candidate profile: Holding a PhD in neuromorphic electronics, IMC circuits or a related discipline, you demonstrate confirmed skills in integrated circuit design (Cadence Virtuoso) based on emerging memory devices. Proficiency in Python and spiking neural network simulation is required. Scientific rigor, autonomy, the ability to bridge the device, circuit and system levels, and fluent technical English are necessary. A strong interest in ferroelectric memories, neuromorphic computing and bio-plausible learning rules is essential.

Application: Please submit your CV, list of publications and letters of recommendation. 

Supervisors: Pr. Yann Beilliard (UGA, LTM), Dr. Elena-Ioana Vatajelu (CNRS, TIMA) 

Contact: yann.beilliarduniv-grenoble-alpes.fr (yann[dot]beilliard[at]univ-grenoble-alpes[dot]fr)