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III-V based Logical Devices

Since 2014, we have focused our efforts on optimizing CVD growth parameters for the growth of axial Si/SiGe heterostructures in nanowires and their integration into tunneling transistors. We were first interested in qualifying the stiffness of the interfaces by physicochemical measurements (HAADF-STEM, Auger) in collaboration with our partners (C2N-Paris, CEA-PFNC-Grenoble).

The asymmetry observed for these 2 interfaces could be adjusted using a kinetic model in collaboration with IOFFE Institute-St Petersburg. We have studied the electrical properties of horizontal nanowire channel transistors with a semi-clad gate. Thanks to this Si/Si/SiGe structure, we have succeeded in increasing the density of the current passing. This improvement in the performance of our devices is mainly due to the reduction in the gap of the source material (SiGe). In particular, we obtained a slope below the threshold of around 135 mV/dec at room temperature. This research work was carried out as part of the ANR international NAHDEVI project in close collaboration with IMEP-LAHC, SiNaPS-CEA Grenoble and the University of Vienna in Austria.

More recently, we have been interested in the growth of GeSn nanowires which show Sn enrichment on the nanowire surface and a core-shell radial distribution. Concerning 3D integration, we have produced SiGe nanowire channel transistors connected to CMOS logic in close collaboration with LN2 at the University of Sherbrooke and ST Microelectronics. All of the activities on nanowires have been the subject of several publications and numerous presentations at national and international conferences.

In the field of III-V and 2D materials for nano/opto-electronics, we have focused on a few major issues, by developing deposition processes over a large surface (300mm diameter S substrate) and CMOS compatible, this which allows: (i) a saving of critical materials (In and Ga for example) by using ultra-thin layers instead of massive materials (replacement of InP and GaAs substrates), (ii) the development of techniques and processes large surface development (MOVPE 300 mm), (iii) hetero-epitaxy on silicon and integration on CMOS platform in nano and optoelectronic components. We have obtained major results in this area by studying the growth of GaAs and GaSb. We have developed a surface preparation process coupling plasma cleaning with annealing under dihydrogen which allows the formation of biatomic steps and thus eliminate crystal defects called antiphase walls on nominal Si(100) substrates. We are the only group in the world to master this technology in a controlled and reproducible manner, without Si buffer growth or substrate structuring. It thus becomes possible to obtain thin layers (140 nm) of GaAs epitaxied on silicon without antiphase walls.

In the field of dielectrics and more precisely metal oxides, we studied the growth by ALD of TiO2 in its rutile phase, the one which has the highest dielectric constant. The major interest of this dielectric in microelectronics and more broadly in electronics lies in the exploitation of this high constant to produce capacitors with high capacity density for applications in DRAM (Dynamic Randon Access Memory), supercapacitors, switching power supplies, etc. More precisely, MIM (Metal-Insulator-Metal) structures were produced on a 3D substrate, i.e. comprising holes with inclined sides to facilitate the conformal deposition of the MIM structure. We have thus shown the possibility of producing 3D MIM structures based on TiO2 which have a capacitance of up to 185 nF/mm2, an unprecedented density value. We also used conduction mode atomic force microscopy (C-AFM) under ultra-high vacuum to study the degradation mechanisms of gate oxides of MOS transistors as well as the switching mechanisms of resistive memories at the nanoscale. This method makes it possible to study the electrical properties of the oxide after its deposition without manufacturing devices.

Submitted on March 14, 2024

Updated on March 14, 2024